This invention relates generally to the field of high speed digital communications. More specifically, this invention relates to a digital communications modulator which accommodates a wide baud rate range.
An infrastructure of high speed digital communications receivers has developed. A wide range of modulation formats is accommodated throughout this infrastructure. In addition to meeting the needs of this infrastructure, a need exists to perform digital communications at ever faster data rates, including rates faster than those commonplace in the high speed digital communications receiver infrastructure. A digital communications modulator able to accommodate such a wide range of data rates would be highly desirable.
One technique for increasing data rates is to communicate a greater amount of data per unit or baud interval and another technique is to increase the rate at which symbols are communicated (i.e. the baud or baud rate). Communicating a maximum amount of data per baud interval is particularly desirable when digital communications are transported through an RF medium because bandwidth does not increase in response to increases in the amount of data per baud interval, assuming transmission power levels remain constant. However, a point of diminishing returns is quickly reached where increasing the amount of data per baud interval leads to excessive bit error rates. Accordingly, to further increase data rates, baud rates need to increase, and in RF applications the increased baud rates are desirably supported by increasing the bandwidth requirements no more than absolutely necessary.
Conventional modulators operate at a clock rate greater than or equal to the baud rate. In other words, data processing modulation functions, such as encoding, phase mapping, pulse shaping, peak power reduction, preceding, and the like, occur in a pipe-lined fashion at a clock rate at or above the baud rate. From a maximum baud rate achievable with a maximum clock rate, lower baud rates may easily be achieved simply by lowering the clock rate.
Modern high speed digital communications modulators perform a large amount of digital processing functions using a massive number of active semiconductor devices. Accordingly, such modulation processing functions are desirably implemented, as much as possible, using very large scale integration semiconductor process technologies. For example, complementary metal oxide semiconductor (CMOS) is currently a desirable semiconductor process technology because of its low power, low cost, and high density integration properties. Unfortunately, the maximum clock rate supported by the CMOS process results in an undesirably low baud rate using the conventional technique of processing data using a clock rate greater than or equal to the baud rate.
One technique for increasing the baud rate would be to use an alternate semiconductor process technology which supports higher clock rates. Unfortunately, this approach has a highly undesirable consequence. The currently available semiconductor technologies supporting clock rates higher than those supported by the CMOS process tend to consume more power than the CMOS process and tend to be much more expensive than the CMOS process. Moreover, such processes tend to support a lower degree of integration than CMOS. In other words, fewer active semiconductor devices can be placed on an integrated circuit. Consequently, numerous, expensive, high power integrated circuits would be required to perform the same digital communications modulation functions at a higher clock rate that may otherwise be performed at a lower clock rate in a single, low power, low cost CMOS integrated circuit.
Accordingly, a high speed digital communications modulation processing architecture which supports a variety of baud rates, including a baud rate in excess of the clock rate, is needed. Such an architecture could be implemented using a low cost, low power, highly integratable semiconductor process technology, such as CMOS to form a low power, low cost, highly reliable modulator or modulator family.
Accordingly, it is an advantage of the present invention that an improved high speed digital communications modulator is provided.
Another advantage is that a high speed digital communications modulator performs digital communications processing to achieve a baud rate in excess of the clock rate.
Another advantage is that a high speed digital communications modulator includes two integrated circuit (IC) modulation processors which operate in parallel.
Another advantage is that a digital communications IC modulation processor may be used alone to support baud rates up to a maximum clock rate for the IC modulation processor, and may be used in parallel with another such IC modulation processor to support baud rates in excess of the maximum clock rate for the IC modulation processor.
Another advantage is that a high speed digital communications modulator is provided in which the pulse shaping function is performed using two half-filters which may be located on the same IC modulation processor or on different IC modulation processors.
Another advantage is that an RF power amplifier linearizer is preceded by an interpolator that increases the number of samples per baud interval so that spectral components in excess of the baud rate introduced by the linearizer are not substantially aliased back into the communications passband.
The above and other advantages of the present invention are carried out in one form by a digital communications modulator that includes a data splitter configured to split an input data stream into a plurality of input substreams. A plurality of phase mappers couple to the data splitter, and each of the phase mappers is configured to generate a phase-mapped substream from one of the input substreams. A plurality of pulse shaping filters couple to the plurality of phase mappers, and each of the pulse shaping filters is configured to generate a shaped substream from one of the phase-mapped substreams. A substream combiner couples to two of the plurality of pulse shaping filters. The substream combiner combines two of the shaped substreams into a combined shaped substream.
The above and other advantages are carried out in another form by a digital communications modulator having a phase mapper configured to generate a phase-mapped data stream. The modulator also has a pulse shaping filter that is configured to generate a shaped data stream from the phase-mapped data stream. An interpolator has an input responsive to the shaped stream and has an output. A radio frequency (RF) power amplifier linearizer has an input responsive to the interpolator output.
The above and other advantages are carried out in another form by a digital communications modulator that includes a phase mapper configured to generate a phase-mapped data stream. The modulator also includes a tapped delay line that has a plurality of cascaded delay stages and an input adapted to receive the phase-mapped data stream. A coefficient scaling section couples to the tapped delay line. A summing section couples to the coefficient scaling section, and a multiplexing section couples to the tapped delay line to selectively enable and disable a portion of the delay stages. The phase mapper, tapped delay line, coefficient scaling section, and summing section are located on a common semiconductor substrate, and the multiplexing section is controlled by signals supplied externally from the substrate.